1. Field of the Invention
This invention relates to a bus bridge circuit connecting two PCI buses or other buses to transfer data between two buses, a bus connection system, and a data error notification method for the bus bridge circuit, and in particular relates to a bus bridge circuit which provides notification of parity errors in data transfers between two buses, a bus connection system, and a data error notification method for the bus bridge circuit.
2. Description of the Related Art
Various functional devices are connected by buses in computer systems to realize various functions. With the spread of personal computers in recent years, a controller and similar are constructed by connecting functional devices developed for personal computers with a Peripheral Component Interconnect (PCI) bus.
On the other hand, when devices with different functions are connected by a bus, it is effective to provide bridge circuits in the bus between devices. FIG. 7 is a drawing of the conventional configuration of a bridge circuit (PCI bridge circuit) connected to PCI buses.
The PCI bridge circuit 202 is connected to two PCI buses 300, 400, and performs data transfer between a PCI device 200 connected to the PCI bus 300, and a PCI device 204 connected to the PCI bus 400. The PCI bridge circuit 202 comprises a FIFO (fast-in fast-out) buffer which stores transfer data, and a control circuit which performs control as the target as seen by a PCI device, and also performs control as the master as seen by the other PCI device.
Here, when a read request is issued from the PCI device 200 to the PCI device 204, and the read data is transferred from the PCI device 204 to the PCI device 200 (called a “read operation”), a read request is issued from the PCI device 200 to the PCI bridge circuit 202. Then, the PCI bridge circuit 202 issues a read request to the PCI device 204, and data from the PCI device 204 is pre-fetched to the FIFO buffer via the primary-side PCI bus 400.
On the other hand, the PCB bus protocol provides a CBE (Command Byte Enable) function, so that the validity of data of the PCI bus width (for example, 64 bits=8 bytes, 32 bits=4 bytes) can be specified in byte units. That is, the data bits of the PCI bus width can be made valid or invalid in byte units, according to the number of data bits required by a PCI device connected to the PCI bus, to acquire the required transfer data from parallel transfer data.
Using this CBE function, for example, in the case of a PCI bus of width 32 bits, a 4-bit CBE signal is issued from the initiator (master) PCI device to control the validity/invalidity of the data in byte units.
Further, in order to protect this CBE signal and the read data (AD signal), during a read operation the XOR (exclusive-OR) of the CBE signal issued from the initiator PCI device to the target PCI device and the bits of all the data outputted by the target PCI device is taken, a parity signal (1 bit) is generated, and the parity signal is sent to the target PCI device.
For example, when performing a read operation across the PCI bridge 202 of FIG. 7, the parity for the PCI bus 400 on the target side is generated by XOR'ing the CBE signal issued by the PCI bridge circuit 202 and the read data of the PCI device 204, and the parity for the PCI bus 300 on the initiator side is generated by XOR'ing the CBE signal issued by the PCI device 200 and the read data outputted by the PCI bridge circuit 202.
In the PCI devices 300, 400 on both sides of the PCI bridge circuit 202, the read data has the same value, so that if both CBE signals are the same, the parity will be the same, and it is sufficient for the PCI bridge circuit to transmit to the PCI device 200 the unmodified parity signal received from the PCI device 204, without generating a parity signal.
However, as stated above, because the CBE signal can be changed, in the prior art the PCI bridge circuit 202 generates the parity of the PCI device 200 on the initiator side by XOR'ing the CBE signal issued by the PCI device 200 and the read data outputted by the PCI bridge circuit 202.
On the other hand, when the PCI bridge circuit 202 pre-fetches data from the PCI device 204, the value of the CBE signal on the initiator side cannot be predicted, so that during reading the CBE signals from the PCI bridge circuit 202 are all set to valid (CBE signals are all “0”), to enable accommodation of different patterns of valid bits determined by CBE signals from the initiator-side PCI device 200.
That is, there are cases in which the CBE signal values are different on the two sides of the PCI bridge circuit 202. Consequently when the PCI bridge circuit 202 receives a read request from the PCI device 200, if there is a parity error in data pre-fetched from the PCI device 204, the erroneous pre-fetched data and the CBE signal are used to generate the parity, and so there is the problem that the PCI device 200, on receiving this parity signal, cannot recognize the parity error.